FPGA Design Engineer
EnErgo*
FPGA Design Engineer
Samenvatting
Wat krijg je?
Wat ga je doen?
- Translate requirements into VHDL designs
- Author self-checking testbenches and UVM
- Optimize various hardware-software boundaries
- Pitch proactive architectural improvements
- Inject new methodologies into stack
Wat verwachten wij?
- 4+ years experience with complex R&D designs
- Mastery of VHDL and Vivado or Quartus
- Experience with high-end simulation platforms like QuestaSim
- Knowledge of processor and bus-system architectures
Volledige vacaturetekst
We are building the next generation of distributed, ultra-low latency control stacks for massive-scale compute architectures. This role puts you at the physical-to-digital frontier, orchestrating thousands of nodes with nanosecond-level synchronization. You will shape architecture and influence high-level technical decisions while collaborating with world-class scientists. If you thrive on extreme ownership and technical sparring, come define the future of high-frequency data processing. Ready to conquer the ultimate scaling challenge? Check out the full mission.
We are building the next generation of distributed, ultra-low latency control stacks for massive-scale compute architectures. Our technology powers world-class research facilities and industrial systems globally, pushing the absolute limits of synchronization, high-frequency analog interfacing, and real-time data processing.
Imagine orchestrating thousands of parallel, interconnected nodes with nanosecond-level deterministic synchronization and all-to-all connectivity. If you want to solve the ultimate design and verification scaling challenges at the physical-to-digital frontier, this is where you belong.
You will collaborate daily with electrical engineers, embedded software teams, and domain scientists. We value extreme ownership; you’ll have a direct hand in shaping architecture, influencing high-level technical decisions, and constantly injecting new methodologies from the ASIC/FPGA industry into our stack.
Your Role:Architect & Implement: Translate complex, high-throughput requirements into robust VHDL designs.
Verify at Scale: Author self-checking testbenches at the module level and contribute to scaling our top-level UVM verification environments.
Integrate & Optimize: Dig into internal and third-party vendor documentation (advanced FPGAs, high-speed ASICs) to optimize hardware-software boundaries.
Collaborate & Mentor: Act as a technical sparring partner to a diverse digital design and embedded team, proactively pitching architectural improvements.
4+ years of experience shipping complex designs in a fast-paced, cutting-edge R&D environment.
Deep mastery of VHDL and the Xilinx Vivado or Intel Quartus toolchains.
Hands-on experience with high-end simulation platforms (e.g., QuestaSim).
Strong grasp of processor and bus-system architectures (e.g., AMBA AXI, Avalon).
Fluent with Git and scripting for automation (Python, Tcl, Shell).
Hands-on experience with Xilinx Zynq / UltraScale+ / RFSoC architectures.
Familiarity with (System)Verilog and advanced verification frameworks (UVM, OSVVM, Cocotb).
A track record of conquering complex timing closure issues.
Background in DSP, microarchitecture design, or C/C++ / Linux kernel development.
Exposure to cryogenic, RF, or advanced physics control instrumentation.
Over de werkgever
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